1. Field of the Invention
This invention relates to the field of bipolar junction transistor (BJT) structures, and particularly to methods of reducing the width of a BJT or HBT device's emitter fingers.
2. Description of the Related Art
Power BJTs typically achieve a high current carrying capacity by dividing the device's emitter and emitter contact into a number of separate “fingers”. For best performance, the width of each emitter finger is made as narrow as possible; this enables base resistance (RB) and base-collector capacitance (CBC) to be reduced, which improves the device's RF performance. Heat dissipation is also improved with narrow emitter fingers. Access to each emitter finger is provided with a via formed through an intervening inter-level dielectric layer.
The narrowness of an emitter finger is limited by the minimum dimension associated with the fabrication process used to fabricate the device, and by the process's minimum alignment tolerances. For example, if the minimum process dimension is 0.6 μm, then the minimum width of the vias to each finger is 0.6 μm. Then, if the fabrication process has an alignment tolerance of 0.3 μm, the minimum emitter width (WE) is 1.2 μm (0.3 μm+1.2 μm+0.3 μm). This width may result in unacceptable RF and/or thermal performance for the resulting device.
One solution to this problem is found in the silicon semiconductor industry: a T-shaped emitter is fabricated from polycrystalline silicon; forming the via at the top of the T allows one of the alignment tolerances to be avoided, thereby enabling a narrower emitter width. However, for devices based on compound semiconductors such as indium phosphide (InP)—typically employed for operation at very high frequencies—this approach is not feasible. The high temperature processing required to fabricate the polycrystalline silicon emitter is incompatible with the processes needed to fabricate compound semiconductors, and no convenient analog to polysilicon exists in compound semiconductors.